The CTIA (Capacitor Transimpedance Amplifier) is utilized in infrared and other sensing applications to integrate the current generated from a radiation detector for a specified period of time, referred to as the integration time. Referring to FIG. 1A, the CTIA of a particular unit cell contains a high gain inverting amplifier or driver with a capacitor in the feedback loop (C.sub.FB). The inverting amplifier typically contains, as a minimum, two active transistors or MOSFETs (metal oxide semiconductor field effect transistors). A first transistor or MOSFET is used to provide a constant current source (typically referred to as the load), while the second transistor or MOSFET is used to implement the driver itself. A reset switch is placed across the feedback capacitor and is closed to discharge the capacitor and is then opened to begin the integration time. The output voltage of the CTIA is proportional to the product of the detector current (I.sub.D) and the integration time, and is inversely proportional to the value of the feedback capacitor C.sub.FB. The input voltage is maintained near the reset value by the feedback loop, which maintains a nearly constant bias on the radiation detector. At the end of the integration time the output voltage is sampled by momentarily closing an output multiplexer (MUX) switch, the reset switch is closed, and the CTIA is ready for the next integration.
In a conventional implementation, a two dimensional array of detectors and unit cells are arranged in a row and column (x by y) matrix (only one unit cell of one column is depicted in FIG. 1A). Typically the MUX switch of the unit cells are closed and then opened one after another to readout in sequence the x unit cell outputs from each of the rows connected to a single one of the y column output lines. Also connected to the column line may be an input of a sample and hold (S/H) circuit (not shown), followed by a voltage follower (not shown). The output voltages may eventually be converted to a digital form and then operated on by a data processing system for performing any desired image processing, or to simply store the image(s) for subsequent transmission to another location.
The CTIA has been found to be one of the circuits best suited for the low noise amplification of signals from infrared detectors. However, the conventional CTIA requires a constant current to keep it active throughout the signal integration cycle, and also requires a significant amount of circuit layout area to accommodate all of the circuitry normally associated with its implementation. The constant current requirement results in constant power dissipation, which in turn can place a considerable load on the (cryogenic) cooling system that is normally required when operating high performance IR detectors. Furthermore, the significant power dissipation, in combination with the significant circuit area required to layout the CTIA, tends to restrict the number of unit cells that it is practical to place within a given chip. As such, the number of detector sites is limited, as is the minimum spacing between detector sites, resulting directly in a limit on the achievable image resolution.
Also, it is known in the art to perform a correlated double sampling of the detector output signal, wherein the detector output at the beginning of an integration period is clamped or stored, and is subtracted from the integrated charge during the integration period. A resulting difference signal is what is sampled and readout at the end of the integration period. However, in conventional practice the provision of correlated double sampling in the unit cell requires the addition of large analog transistors, thereby further increasing power consumption and the required unit cell circuit area.
Reference with regard to various aspects of charge amplifiers and CTIAs may be had to the following U.S. Patents, namely U.S. Pat. No. 4,956,716, "Imaging System Employing Charge Amplifier", by Hewitt et al.; U.S. Pat. No. 5,043,820, "Focal Plane Array Readout Employing One Capacitive Feedback Transimpedance Amplifier For Each Column", by Wyles et al.; U.S. Pat. No. 5,602,511, "Capacitive Transimpedance Amplifier Having Dynamic Compression", by Woolaway; and U.S. Pat. Nos. 4,978,872 and 4,786,831, both entitled "Integrating Capacitively Coupled Transimpedance Amplifier", by Morse et al. The disclosures of these U.S. Patents are incorporated by reference herein in their entireties.
Of particular interest is the two stage amplifier illustrated in FIG. 4 of U.S. Pat. No. 4,956,716, by Hewitt et al., a portion of which (the first stage) is depicted herein in FIG. 1B. The first stage includes two N-channel MOSFETs (each having a gate (G), source (S) and a drain (D)) which are powered by electric energy stored in two capacitors C1 and 3C1. The designation `3C1` indicates that the capacitance value of this capacitor is three times that of C1. The ratio of these capacitances (i.e., 3) determines the voltage gain of the first stage. The second stage is implemented in a similar fashion.
However, this particular charge amplifier, while being well suited for its intended application(s), is not a CTIA, and does not include, for example, the feedback capacitance (C.sub.FB) loop as depicted in FIG. 1A.